Digital Verification Engineer, Crypto & Security

We are actively expanding the Crypto & Security Competence Centre (CCC&S) at NXP and we have new opportunities in our team for digital verification engineers working on next-generation security technologies such as:Post-Quantum Cryptography (PQC) IPSecure SoC subsystems, including next-generation roots of trustHigh-assurance cryptographic accelerators for future platformsAt CCC&S, we are also driving a significant transformation in how hardware is designed and verified by integrating AI directly into IC design and verification flows. The role is blended with traditional verification methods whilst the AI agents are being developed. The role is blended with traditional verification methods whilst the AI agents are being developed.

Driven Verification – What You’ll Be Part OfIn this role, you will contribute to a step-change in verification capability through:AI-driven verification automation – reducing regression effort while maintaining full coverageIntelligent debug and analysis – accelerating bug discovery and root-cause identificationAutomated test and vPlan generation – improving consistency and reducing human errorWe are also actively developing advanced capabilities including:AI-assisted RTL understanding and test explanationConversational debug interfaces for waveform and design interactionAI-driven coverage closure and test prioritisationThis is not a future vision—this transformation is already underway within CCC&S workflows.

Why This Role Stands OutWork on cutting-edge cryptography technologies critical to future cybersecurityHelp define how AI transforms verification workflows and methodologiesJoin a growing organisation where your input shapes tools, processes, and technical directionTake ownership of high-visibility, complex projects from concept to silicon

Your Responsibilities

• Verification of digital hardware architectures. Creating, reviewing, and maintaining verification plans, and tracking verification progress. Specifying and developing verification strategies, tests, and environments for security features and hardware co‑processors. Working with emerging verification methodologies and introducing them into existing verification flows. Your ProfileBSc., or MSc., degree in Electronics or Electrical Engineering. Some experience with SystemVerilog for testbench development and verification. Some experience in UVM (Universal Verification Methodology), including component creation, sequences, drivers, monitors, and scoreboards. Solid understanding and practical use of Constrained Random Verification techniques. Experience with Metrics‑Driven Verification, including functional coverage and verification planning.
  Ability to write SystemVerilog Assertions (SVA) for protocol and design checking. Demonstrated success in achieving Coverage Closure across functional and code coverage metrics. Experience analysing coverage results and refining test strategies to close gaps. Strong debugging skills across simulations and complex verification environments. Knowledge of Formal Verification methods would be advantageous.If you're excited by the opportunity to work at the intersection of hardware, security, and AI, and want to contribute to technologies that will define the next decade, we invite you to apply!