Senior Compiler Engineer

ppZürich, Switzerlandbr/Seniority: 5+ years (systems, compilers, or embedded) /p pJoin the core software team that turns ComputeRAM into something developers love to use. You will design and ship a software integration kit, build the software library components that sit between applications and hardware, develop compiler passes that lower NN/DSP ops to our primitives, and own a solid benchmarking pipeline.

You will work closely with silicon and equally closely with users, moving from prototype to production with clean code, clear documentation, and measurable speed and energy gains. /p h3bWhat you’ll do /b /h3 ul liDesign and implement embedded software libraries and low-level runtime for ComputeRAM-enabled platforms. /li liDevelop and maintain the compiler path (MLIR/LLVM passes, code generation, kernels) that maps AI and DSP primitives and related operations to our hardware. /li liDevelop and refine a benchmarking and profiling framework that incorporates reproducible tests, dashboards, and regression gates. /li liStrengthen build, test, and CI so releases are predictable and artifacts are easy to consume. /li liCollaborate with hardware, architecture, and customer-facing teams; write precise specs and documentation; turn feedback into roadmap items. /li /ul h3bOutcomes (first 18 months)

/b /h3 ul liA production-ready driver + runtime stack for at least one MCU target and one accelerator-class target. /li liA working compiler path with visible wins in latency and energy on representative models, documented end-to-end. /li liA stable benchmark suite with automated reports and performance guards integrated in CI. /li liDeveloper-quality docs, examples, and reference projects that make first use smooth for partners. /li /ul h3bRequirements /b /h3 ul li5+ years building low-level software or compilers; strong C++ and Python; you have shipped production code. /li liHands-on experience with embedded systems and compiler design /li liSolid systems understanding. memory and concurrency fundamentals /li liComfortable reading hardware datasheets and working at the HW/SW boundary. /li liEvidence of performance work (profiling, tracing, optimization) on embedded or accelerator

targets. /li liClear writing, good documentation habits, and a collaborative approach. /li /ul h3bNice to have /b /h3 ul liExperience deploying deep-learning workloads on edge devices; familiarity with TensorFlow Lite for Micro, TVM, or IREE. /li liHPC exposure (DirectML, OpenCL, CUDA) or DSP algorithm implementations. /li liCI/CD depth and packaging for developer kits, utilizing GitHub Actions or a similar tool. /li liQuantization and fixed-point experience for edge inference. /li /ul h3Interview flow (indicative) /h3 ol li30-min intro with HR (role/context) /li liFirst Technical deep dive /li liSecond Technical Deep Dive /li li(Optional) Third Technical Deep Dive /li liSystems/product conversation with management /li /ol /p