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Senior Software Engineer (Processor Software Stack)

Veröffentlicht am

Arbeitsort
40213 Düsseldorf, Nordrhein-Westfalen, Deutschland

Stellenbeschreibung

We are looking for a Senior Software Engineer who is at home across our processor software from ported libraries and the compiler down to bare-metal and operating systems. Your team will: develop our software stack, including compiler, mapping tools, low-level tooling, simulation and debug infrastructure; write bare-metal, firmware and OS-level software for our RISC-V SoC; implement and optimise signal-processing and inference kernels under real-time constraints; bring up, test and port software on pre-silicon platforms and on silicon, including low-level hardware tests; and work in a close feedback loop with our hardware designers.

We are looking for

  • Strong C, modern C++ (C++17/20, STL, Boost) and Python.
  • A solid foundation in algorithms and in hardware/software system architecture.
  • Experience working close to the hardware, with a good understanding of system-on-a-chip design, processor architecture and microarchitecture, and some familiarity with RTL and hardware design.
  • Experience with agentic programming.
  • You know your way around all of these fields, and go deep in at least one:
  • compiler development and code generation
  • low-level tooling, simulation and performance analysis
  • low-level embedded or systems software, operating systems and real-time
  • signal processing, numerical computation and ML inference

Master’s degree (or equivalent experience) and 10+ years of relevant experience.

Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.

Nice to have

  • Parallel and data-flow execution models: SIMT, predicated execution, branch divergence.
  • Mapping and optimisation algorithms: graph algorithms, place-and-route / EDA, CGRA or FPGA mapping, ILP solvers.
  • Kernel-level optimisation: vectorisation, data layout, memory hierarchy, fixed-point and quantised arithmetic.
  • Post-silicon validation and hardware bring-up, including directed and random test generation.
  • Porting code to new platforms.
  • Exposure to: RISC-V, LLVM, CUDA, OpenCL, Verilog, Verilator, QEMU, GDB, JTAG and on-chip debug, OpenSBI, bootloaders, HAL, Linux kernel and device drivers, device tree, Zephyr, Yocto/OpenEmbedded, BLAS/LAPACK/OpenBLAS.

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